Sub Engine Background registers. More...

Macros
#define	BACKGROUND_SUB (((bg_attribute )0x04001008))
	Overlay for sub screen background attributes. Setting the properties of this struct directly sets background registers.

#define	BG_BMP_RAM_SUB(base) ((u16)(((base)0x4000) + 0x06200000))
	A macro which returns a u16* pointer to background graphics ram (Sub Engine)

#define	BG_MAP_RAM_SUB(base) ((u16)(((base)0x800) + 0x06200000))
	A macro which returns a u16* pointer to background map ram (Sub Engine)

#define	BG_OFFSET_SUB ((bg_scroll *)(0x04001010))
	Overlay for sub screen background scroll registers. Setting the properties of this struct directly sets background registers.

#define	BG_TILE_RAM_SUB(base) ((u16)(((base)0x4000) + 0x06200000))
	A macro which returns a u16* pointer to background tile ram (Sub Engine)

#define	BGCTRL_SUB ( (vu16*)0x4001008)
	Access to all Sub screen background control registers via: BGCTRL[x] GBATEK Reference

#define	REG_BG0CNT_SUB ((vu16)0x4001008)
	Background 0 Control register (sub engine) GBATEK Reference

#define	REG_BG0HOFS_SUB ((vu16)0x4001010)
	Background 0 horizontal scroll register (sub engine)

#define	REG_BG0VOFS_SUB ((vu16)0x4001012)
	Background 0 vertical scroll register (sub engine)

#define	REG_BG1CNT_SUB ((vu16)0x400100A)
	Background 1 Control register (sub engine) GBATEK Reference

#define	REG_BG1HOFS_SUB ((vu16)0x4001014)
	Background 1 horizontal scroll register (sub engine)

#define	REG_BG1VOFS_SUB ((vu16)0x4001016)
	Background 1 vertical scroll register (sub engine)

#define	REG_BG2CNT_SUB ((vu16)0x400100C)
	Background 2 Control register (sub engine) GBATEK Reference

#define	REG_BG2HOFS_SUB ((vu16)0x4001018)
	Background 2 horizontal scroll register (sub engine)

#define	REG_BG2PA_SUB ((vs16)0x4001020)
	Background 2 Affine transform (sub engine)

#define	REG_BG2PB_SUB ((vs16)0x4001022)
	Background 2 Affine transform (sub engine)

#define	REG_BG2PC_SUB ((vs16)0x4001024)
	Background 2 Affine transform (sub engine)

#define	REG_BG2PD_SUB ((vs16)0x4001026)
	Background 2 Affine transform (sub engine)

#define	REG_BG2VOFS_SUB ((vu16)0x400101A)
	Background 2 vertical scroll register (sub engine)

#define	REG_BG2X_SUB ((vs32)0x4001028)
	Background 2 Screen Offset (sub engine)

#define	REG_BG2Y_SUB ((vs32)0x400102C)
	Background 2 Screen Offset (sub engine)

#define	REG_BG3CNT_SUB ((vu16)0x400100E)
	Background 3 Control register (sub engine) GBATEK Reference

#define	REG_BG3HOFS_SUB ((vu16)0x400101C)
	Background 3 horizontal scroll register (sub engine)

#define	REG_BG3PA_SUB ((vs16)0x4001030)
	Background 3 Affine transform (sub engine)

#define	REG_BG3PB_SUB ((vs16)0x4001032)
	Background 3 Affine transform (sub engine)

#define	REG_BG3PC_SUB ((vs16)0x4001034)
	Background 3 Affine transform (sub engine)

#define	REG_BG3PD_SUB ((vs16)0x4001036)
	Background 3 Affine transform (sub engine)

#define	REG_BG3VOFS_SUB ((vu16)0x400101E)
	Background 3 vertical scroll register (sub engine)

#define	REG_BG3X_SUB ((vs32)0x4001038)
	Background 3 Screen Offset (sub engine)

#define	REG_BG3Y_SUB ((vs32)0x400103C)
	Background 3 Screen Offset (sub engine)

Detailed Description

Sub Engine Background registers.

Macros

Detailed Description